1. Field of the Invention
The present invention relates to an insulated-gate field effect transistor (hereinafter called IGFET) and a method for manufacturing the same.
2. DESCRIPTION OF THE PRIOR ART
One of the known IGFET's was obtained through the steps of forming, in a semiconductor substrate of one conductivity type, drain and source regions of the opposite conductivity type, forming a thin insulating gate film on the surface of the semiconductor substrate between these regions, thereafter forming apertures in an insulation coating film covering the source and drain regions, providing lead out ohmic electrodes from the drain and source regions through the apertures, and also providing a gate electrode on the gate film. However, such an IGFET becomes large in geometrical configuration, and hence, prevents the enhancement of degree of integration of monolithic semiconductor ICs. Also, the gate electrode and the drain and source regions, respectively, overlap with each other at the side end portions of the thin insulating gate film, and therefore, there is a disadvantage in that the gate electrode is associated with a stray capacitance and thus improvements in the electric performance of such types of IGFET are prevented.
On the other hand, in order to improve the disadvantage of the above-described IGFET, a silicon-gate type IGFET was proposed which can be attained through the steps of forming a thin insulating gate film on a surface of a semiconductor substrate of one conductivity type, depositing a polycrystalline silicon film on the insulating gate film by vapor growth, selectively etching this polycrystalline silicon film to form a gate electrode pattern, diffusion an impurity of the opposite conductivity type into the gate electrode of polycrystalline silicon and into the substrate by using the gate electrode as a mask to form drain and source regions of the opposite conductivity type in the substrate and providing ohmic electrodes for the drain and source regions. The resultant silicon-gate IGFET has a gate electrode self-aligned with the source and drain regions, so that there is no substantial overlap therebetween. If the channel length is shortened for the purpose of enhancing the operation speed, however, the plane configuration of the gate electrode becomes correspondingly narrow, or in other words, it is necessary to select one edge of the polycrystalline silicon film to be used as a gate electrode equal to the small channel length, and accordingly the internal resistance of the gate electrode is necessarily increased, so that restriction imposed upon the desired high speed operation. Moreover, there is a topological restriction in that the gate electrode must be necessarily led out in the direction of the channel width.
This restriction has served as a bar against enhancement of the degree of integration of the semiconductor monolithic integrated circuit employing a large number of IGFETs in which source and drain regions are formed by self-alignment with respect to a gate electrode. More particularly, when the above-mentioned silicon gate type IGFET is normally used with a wiring layer of metal having a low specific resistance such as aluminum or the like connected to a silicon gate electrode, variations of the threshold voltage of the IGFET during use are caused when a silicon gate electrode connects to a metal wiring layer above a gate insulator film. Therefore, it is necessary to electrically lead out the silicon gate electrode to the region where the gate insulating film is not present thereunder, that is, to the region above the thick field insulating film, by means of conductive polycrystalline silicon which forms the gate electrode, and to connect ohmically the gate electrode to the metal wiring layer at that region. However, in view of the heretofore known method for manufacturing a silicon gate IGFET, the gate electrode consisting of the polycrystalline silicon film cannot be extended easily over the drain (source) region in a three-dimensional crossing form, and hence there the topological restriction that the gate electrode must be lead out in the direction of the channel width. Thus, this restriction has served as a great bar against enhancement of the degree of integration of the semiconductor monolithic integrated circuit employing a large number of transistors of such type.
Moreover, when the gate electrode of the prior art silicon gate IGFET is shaped by subjecting a polycrystalline silicon film to selective wet etching, it is difficult to shorten with good precision the channel length of the IGFET, which largely contributes to its electrical performance, because the precision of the etching is poor. Namely, the polycrystalline silicon film must have a thickness of 5000 A to 8000 A, while upon wet etching of polycrystalline silicon, side-etching is effected in the lateral direction by about one-half of the depth of etching, so that the edge of the etched region takes a tapered shape as side-etched by 2500 A to 4000 A. Furthermore, since the etching speed is increased by the use of a liquid temperature caused by chemical reaction upon etching and thus the amount of the side-etching per se cannot be controlled at good precision, it is a difficult problem to form a predetermined shape of the gate electrode with good precision from a thick polycrystalline silicon form of 5000 A to 8000 A.